Display device

ABSTRACT

A display device is provided. The display device includes a substrate having a first surface and a second surface opposite to the first surface. The display device also includes a first conductive layer disposed on the first surface and a second conductive layer disposed on the second surface. The display device further includes a processing unit disposed on the second surface and is electrically connected to the processing unit and a first connective portion which at least partially disposed in the substrate, and penetrating from the first surface to the second surface, wherein the first conductive layer is electrically connected to the second conductive layer through the first connective portion.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority of China Patent Application No.201710067676.6, filed on Feb. 7, 2017, which claims the benefit ofpriority from a provisional application of U.S. patent application Ser.No. 62/358,177 filed on Jul. 5, 2016 and a provisional application ofU.S. patent application Ser. No. 62/371,252 filed on Aug. 5, 2016, theentireties of which are incorporated by reference herein.

BACKGROUND OF THE INVENTION Field of the Invention

The present disclosure relates to a display device. More particularly,the present disclosure relates to a display device with a substratehaving a connective portion therein.

Description of the Related Art

As digital technologies have progressed, display devices have becomewidely used in all aspects of daily life. For example, they are widelyused in televisions, notebooks, computers, mobile phones, smartphones,and other modern information equipment. In the present display device,the processing unit and the display unit are formed on the same surfaceof the substrate, and the boundary of the non-display area is large, sothat the effective display space is limited.

BRIEF SUMMARY OF THE INVENTION

The present disclosure provides a display device, which includes asubstrate having a first surface and a second surface opposite to thefirst surface. The display device also includes a first conductive layerdisposed on the first surface and a second conductive layer disposed onthe second surface. The display device further includes a processingunit disposed on the second surface and electrically connected to theprocessing unit, and includes a first connective portion at leastpartially disposed in the substrate and penetrating from the firstsurface to the second surface, wherein the first conductive layer iselectrically connected to the second conductive layer through the firstconnective portion.

A detailed description is given in the following embodiments withreference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure may be more fully understood by reading the subsequentdetailed description and examples with references made to theaccompanying drawings, wherein:

FIG. 1 is a cross-sectional view of a display device in accordance withsome embodiments of the disclosure;

FIGS. 2A-2E are illustrations of various stages of a process for forminga connective portion in a substrate, in accordance with someembodiments, wherein FIGS. 2A-2D are perspective views and FIG. 2E is across-sectional view;

FIGS. 3A-3F are illustrations of various stages of a process for forminga connective portion in a substrate, in accordance with someembodiments, wherein FIGS. 3A-3E are perspective views and FIG. 3F is across-sectional view;

FIGS. 4A-4E are cross-sectional views of various stages of a process forforming a substrate having through holes and blind holes, in accordancewith some embodiments;

FIGS. 5A-5B are cross-sectional views of a substrate and through holes,in accordance with some embodiments;

FIG. 6A is a cross-sectional view of a display device, in accordancewith some embodiments;

FIG. 6B is a top view of a circuit layout of a display device shown inFIG. 6A, in accordance with some embodiments;

FIG. 6C is a cross-sectional view taken along line C-C′ of FIG. 6B, inaccordance with some embodiments;

FIG. 6D is a cross-sectional view taken along line D-D′ of FIG. 6B, inaccordance with some embodiments;

FIG. 6E is a cross-sectional view taken along line E-E′ of FIG. 6B, inaccordance with some embodiments;

FIG. 6F is top view of a variation of a display device shown in FIG. 6B,in accordance with some embodiments;

FIG. 7A is a cross-sectional view of a display device, in accordancewith some embodiments;

FIG. 7B is a top view of a circuit layout of a display device shown inFIG. 7A, in accordance with some embodiments;

FIG. 7C is a cross-sectional view taken along line F-F′ of FIG. 7B, inaccordance with some embodiments;

FIG. 7D is a cross-sectional view taken along line G-G′ of FIG. 7B, inaccordance with some embodiments;

FIG. 7E is a cross-sectional view taken along line H-H′ of FIG. 7B, inaccordance with some embodiments;

FIG. 7F is top view of a variation of a display device shown in FIG. 7B,in accordance with some embodiments;

FIG. 8 is a circuit diagram of a demultiplexer, in accordance with someembodiments;

FIG. 9 is a top view of a display device, in accordance with someembodiments;

FIG. 10A is a cross-sectional view taken along line A-A′ of the displaydevice shown in FIG. 9, in accordance with some embodiments;

FIG. 10B is a cross-sectional view taken along line B-B′ of the displaydevice shown in FIG. 9, in accordance with some embodiments;

FIG. 11A is a partial cross-sectional view of a display device, inaccordance with some embodiments;

FIG. 11B is a partial top view of a display device shown in FIG. 11A, inaccordance with some embodiments;

FIG. 12 is a partial cross-sectional view of a display device, inaccordance with some embodiments;

FIG. 13 is a partial cross-sectional view of a display device, inaccordance with some embodiments;

FIG. 14A is a partial cross-sectional view of a display device, inaccordance with some embodiments;

FIG. 14B is a partial top view of a display device shown in FIG. 14A, inaccordance with some embodiments;

FIG. 15A is a partial cross-sectional view of a display device, inaccordance with some embodiments;

FIG. 15B is a partial top view of a display device shown in FIG. 15A, inaccordance with some embodiments;

FIG. 16 is a cross-sectional view of a display device, in accordancewith some embodiments;

FIG. 17 is a cross-sectional view of a display device, in accordancewith some embodiments;

FIG. 18 is a cross-sectional view of a display device, in accordancewith some embodiments.

DETAILED DESCRIPTION OF THE INVENTION

The display device of the present disclosure is described in detail inthe following description. In the following detailed description, forpurposes of explanation, numerous specific details and embodiments areset forth in order to provide a thorough understanding of the presentdisclosure. The specific elements and configurations described in thefollowing detailed description are set forth in order to clearlydescribe the present disclosure. It will be apparent, however, that theexemplary embodiments set forth herein are used merely for the purposeof illustration, and the inventive concept may be embodied in variousforms without being limited to those exemplary embodiments. In addition,the drawings of different embodiments may use like and/or correspondingnumerals to denote like and/or corresponding elements in order toclearly describe the present disclosure. However, the use of like and/orcorresponding numerals in the drawings of different embodiments does notsuggest any correlation between different embodiments. In addition, inthis specification, expressions such as “first material layer disposedon/over a second material layer”, may indicate the direct contact of thefirst material layer and the second material layer, or it may indicate anon-contact state with one or more intermediate layers between the firstmaterial layer and the second material layer. In the above situation,the first material layer may not be in direct contact with the secondmaterial layer.

It should be noted that the elements or devices in the drawings of thepresent disclosure may be present in any form or configuration known tothose skilled in the art. In addition, the expression “a layer overlyinganother layer”, “a layer is disposed above another layer”, “a layer isdisposed on another layer” and “a layer is disposed over another layer”may indicate that the layer is in direct contact with the other layer,or that the layer is not in direct contact with the other layer, therebeing one or more intermediate layers disposed between the layer and theother layer. 0

In addition, in this specification, relative expressions are used. Forexample, “lower”, “bottom”, “higher” or “top” are used to describe theposition of one element relative to another. It should be appreciatedthat if a device is flipped upside down, an element that is “lower” willbecome an element that is “higher”.

The terms “about” and “substantially” typically mean +/− 20% of thestated value, more typically +/−10% of the stated value, more typically+/− 5% of the stated value, more typically +/− 3% of the stated value,more typically +/− 2% of the stated value, more typically +/− 1% of thestated value and even more typically +/− 0.5% of the stated value. Thestated value of the present disclosure is an approximate value. Whenthere is no specific description, the stated value includes the meaningof “about” or “substantially”.

It should be understood that, although the terms first, second, thirdetc. may be used herein to describe various elements, components,regions, layers, portions and/or sections, these elements, components,regions, layers, portions and/or sections should not be limited by theseterms. These terms are only used to distinguish one element, component,region, layer, portion or section from another region, layer or section.Thus, a first element, component, region, layer, portion or sectiondiscussed below could be termed a second element, component, region,layer, portion or section without departing from the teachings of thepresent disclosure.

Unless defined otherwise, all technical and scientific terms used hereinhave the same meaning as commonly understood by one of ordinary skill inthe art to which this disclosure belongs. It should be appreciated that,in each case, the term, which is defined in a commonly used dictionary,should be interpreted as having a meaning that conforms to the relativeskills of the present disclosure and the background or the context ofthe present disclosure, and should not be interpreted in an idealized oroverly formal manner unless so defined.

This description of the exemplary embodiments is intended to be read inconnection with the accompanying drawings, which are to be consideredpart of the entire written description. The drawings are not drawn toscale. In addition, structures and devices are shown schematically inorder to simplify the drawing.

In the description, relative terms such as “lower,” “upper,”“horizontal,” “vertical,”, “above,” “below,” “up,” “down,” “top” and“bottom” as well as derivative thereof (e.g., “horizontally,”“downwardly,” “upwardly,” etc.) should be construed to refer to theorientation as then described or as shown in the drawing underdiscussion. These relative terms are for convenience of description anddo not require that the apparatus be constructed or operated in aparticular orientation. Terms concerning attachments, coupling and thelike, such as “connected” and “interconnected,” refer to a relationshipwherein structures are secured or attached to one another eitherdirectly or indirectly through intervening structures, as well as bothmovable or rigid attachments or relationships, unless expresslydescribed otherwise.

The term “substrate” is meant to include devices formed within atransparent substrate and the layers overlying the transparentsubstrate. All transistor element needed may be already formed on thesubstrate. However, the substrate is represented with a flat surface inorder to simplify the drawing. The term “substrate surface” is meant toinclude the uppermost exposed layers on a transparent substrate, such asan insulating layer and/or metallurgy lines.

At first, referring to FIG. 1, FIG. 1 is a cross-sectional view of adisplay device 1000 in accordance with some embodiments of thedisclosure. The display device 1000 includes a processing unit 10, asubstrate 20 and a display element layer 50. The processing unit 10 mayinclude, but is not limited to, an integrated circuit (IC), amicroprocessor, a memory device, other elements processing signal or acombination thereof. The substrate 20 may be a transparent substrate,such as a glass substrate, a ceramic substrate, a plastic substrate oranother applicable substrate. The substrate 20 may be a hard substrateor a flexible substrate. The display element layer 50 may include, butis not limited to, a gate driver circuit, a data line, a thin filmtransistor, a light-emitting layer, a capacitor, an inductor, a passivemicro-electronic element, an active micro-electronic element or acombination thereof.

In some embodiments, as shown in FIG. 1A, the substrate 20 has a firstsurface 20A and a second surface 20B opposite to the first surface 20A.A first conductive layer 41 is disposed on the first surface 20A, and asecond conductive layer 42 is disposed on the second surface 20B. Theprocessing unit 10 is disposed on the second surface 20B andelectrically connected to the second conductive layer 42. A firstconnective portion is at least partially disposed in the substrate 20,and penetrates from the first surface 20A to the second surface 20B. Thefirst conductive layer 41 is electrically connected to the displayelement layer 50. The processing unit 10 is electrically connected tofirst conductive layer 41 through a first connective portion 30, andthereby the signal from the processing unit 10 is transmitted to thedisplay element layer 50.

Referring to FIGS. 2A-2E, FIGS. 2A-2E are illustrations of variousstages of a process for forming a connective portion penetrating thesubstrate, in accordance with some embodiments. The following processmay be applied in forming the first connective portion in the presentdisclosure, in accordance with some embodiments. At first, referring toFIG. 2A, a first carrier substrate 100 is provided, and multiple pillars110 are disposed on the first carrier substrate 100.

Next, referring to FIG. 2B, a deposition process is used, and thesubstrate 120 is formed on the first carrier substrate 100 such that themultiple pillars 110 protrude on the substrate 120. The material of thesubstrate 120 may be a glass, a photo sensitive material, a polymerresin or another applicable material. The substrate 120 may be a hardsubstrate or a flexible substrate.

Next, the first carrier substrate 100 having multiple pillars 110 isremoved, and the substrate 120 having multiple through holes 130A isformed. Afterwards, as shown in FIG. 2C, the substrate 120 istransferred to a second carrier substrate 101.

Next, as shown in FIG. 2D, a deposition process is used, and aconductive material is filled into the multiple through holes 130A, suchthat multiple first connective portions 130A is formed. Furthermore, adisplay element layer 140 is formed on the substrate 120, and then thesecond carrier substrate 101 is removed.

Finally, as shown in FIG. 2E, the processing unit 141 is disposed, andthe edges of the substrate 120 are bent. According to other embodiments,the edges of the substrate 120 are not bent. In this embodiment, thesubstrate 120 has multiple first connective portions 130. Therefore, theprocessing unit 141 is electrically connected to the display elementlayer 140 or another electronic element through these first connectiveportions 130.

Referring to FIGS. 3A-3F, FIGS. 3A-3F are illustrations of variousstages of a process for forming a connective portion penetrating thesubstrate, in accordance with some embodiments. The following processmay be applied in forming the first connective portion in the presentdisclosure, in accordance with some embodiments. At first, referring toFIG. 3A, a first carrier substrate 100 is provided, and a buffer layer150 is disposed on the first carrier substrate 100. The buffer layer 150may include, but is not limited to, silicon dioxide, silicon nitride,silicon oxynitride or another applicable insulation material.

Next, referring to FIGS. 3B-3C, a deposition process and aphotolithography process are used to form the conductive pillars 160made by a conductive material on the buffer layer 150. A depositionprocess is used to form a substrate 120 on the buffer layer 150, and theconductive pillars 160 are covered by the substrate 120. The conductivepillars 160 may be formed by metal pillars. The substrate 120 may be ahard substrate or a flexible substrate.

Next, as shown in FIG. 3D, the buffer layer 150 and the first carriersubstrate 100 are removed, and the substrate 120 is transferred to asecond carrier substrate 101. As a result, the substrate 120 hasmultiple conductive pillars 160 therein.

Next, as shown in FIG. 3E, a display element layer 140 is formed on thesubstrate 120.

Finally, as shown in FIG. 3F, a processing unit 141 is disposed, and theedges of the substrate 120 are bent. According to other embodiments, theedges of the substrate 120 are not bent. In this embodiment, thesubstrate 120 has multiple first connective portions 160 made byconductive pillars. Therefore, the processing unit 141 is electricallyconnected to a display element layer 140 or other electronic elementsthrough these first connective portions 160.

Referring to FIGS. 4A-4E, FIGS. 4A-4E are cross-sectional views ofvarious stages of a process for forming through holes 200 and blindholes 190 in a substrate, in accordance with some embodiments. At first,as shown in FIG. 4A, a substrate 120 is provided. The substrate 120includes an active region 210, a bending region 220 and a gate drivercircuit region 230. In some embodiments, a half-tone mask 180 is used topattern the substrate 120 so that the substrate 120 has through holes200 and blind holes 190. As shown in FIG. 4A, the through holes 200penetrate through the substrate 120, and the blind holes 190 do notpenetrate through the substrate 120. In some embodiments, the blindholes 190 are formed, but are not limited to, in the bending regions220, and the through holes 200 are formed, but are not limited to, inthe gate driver circuit region 230. The depth of the blind holes 190 isnot limited. In some embodiments, the depth of the blind holes 190 isless than half of the depth of the substrate 120.

Next, as shown in FIGS. 4B-4C, a conductive material (such as a metalmaterial) 240 is deposited into the through holes 200 and the blindholes 190. In some embodiments, when the conductive material 240 isdeposited until half of the depth of the through holes 200 is filled,the substrate 120 is flipped. Afterwards, the conductive material 240 isdeposited until the conductive material 240 is filled on the throughholes 200. As a result, as shown in FIG. 4C, a first connective portions240B filled in the though holes 200 are formed, and the conductive layer240A, made by filling the conductive material into the blind holes 190,is formed. In addition, the first conductive layer 251, used as firstconductive pads on the first surface 120A of the substrate 120, isformed. The second conductive layer 252, used as second conductive padson the second surface 120B of the substrate 120, is formed.

Next, as shown in FIGS. 4D-4E, a display element layer 260 is formed onthe first surface 120A which has the first conductive layer 251. Aprocessing unit 270 is formed on the second surface 120B of thesubstrate 120. The second surface 120B has a second conductive layer252. The display element layer 260 is electrically connected to thefirst conductive layers 251, and the processing unit 270 is electricallyconnected to the second conductive layers 252.

In some embodiments, the conductive layer 240A, the first connectiveportion 240B, the first conductive layer 251 and the second conductivelayer 252 are made of the same conductive material 240. In someembodiments, the conductive material 240 may include copper, aluminum,molybdenum, tungsten, gold, chromium, nickel, platinum, titanium,iridium, rhodium, the above alloys, another applicable metal conductivematerial, or a combination thereof.

FIG. 5A is a cross-sectional view of a substrate 120 and a firstconnective portion 240B, in accordance with some embodiments. As shownin FIG. 5A, the first connective portion 240B has a first width A1 alongthe first surface 120A and a second width A2 along the second surface120B. In some embodiments, the first width A1 is different from thesecond width A2. For example, the first width A1 is greater than thesecond width A2, raising the yield for forming the first connectiveportion and reducing breakage of the connective portion.

FIG. 5B is a cross-sectional view of a substrate 120 and a firstconnective portion 240B, in accordance with some embodiments. As shownin FIG. 5B, the first connective portion 240B has a first width A3 alongthe first surface 120A and a second width A5 along the second surface120B. The first width A3 may be the same as or different from the secondwidth A5. The first connective portion 240B further has a third width A4along a reference plane R. In some embodiments, the reference plane R islocated between the first surface 120A and the second surface 120B, andthe reference plane R is parallel to the first surface 120A. In someembodiments, as shown in FIG. 5B, the reference plane R is locatedbetween the first surface 120A and the second surface 120B and is onehalf of D away from the first surface 120A. D is the thickness of thesubstrate 120. In some embodiments, the first width A3 is different fromthe third width A4. For example, the first width A3 is greater than thethird width A4, raising the yield for forming the first connectiveportion and reducing breakage of the connective portion.

Referring to FIG. 6A, FIG. 6A is a cross-sectional view of a displaydevice 5000, in accordance with some embodiments. The display device5000 includes a processing unit 600, a substrate 610 and a displayelement layer 640. The substrate 610 has a first surface 610A and asecond surface 610B opposite to the first surface 610A. Generally, thefirst surface 610A is called a front side of the substrate, and thesecond surface 610B is called a backside of the substrate. The displayelement layer 640 is disposed on the first surface 610A. A firstconductive layer 631 is formed on the first surface 610A, and a secondconductive layer 632 is formed on the second surface 610B. Theprocessing unit 600 is disposed on the second surface 610B andelectrically connected to the second conductive layer 632. The firstconnective portion 620 is at least partially disposed in the substrate610, and penetrates from the first surface 610A to the second surface610B. The first conductive layer 631 is electrically connected to thesecond conductive layer 632 by the first connective portion 620, andthereby the signal of the processing unit 600 is transmitted to thedisplay element layer 640. The processing unit 600 may include, but isnot limited to, an integrated circuit (IC), a microprocessor, a memorydevice, other elements processing signal, or a combination thereof.

Referring to FIG. 6B, FIG. 6B is a top view of a circuit layout of thedisplay device 5000 shown in FIG. 6A, in accordance with someembodiments. It should be noted that FIG. 6B only illustrates theprocessing unit 600, the first connective portion 620 and other circuitsdisposed in the display element layer 640 for brevity. As shown in FIG.6B, the display element layer 640 includes a gate driver circuit 650 anda data line 670. The gate driver circuit 650 includes a display signalline 650A (such as an input signal circuit) extending along a firstdirection (such as the Y direction) and an output signal circuit 650B(such as a scan line) extending along a second direction (such as the Xdirection). The gate driver circuit 650 and the data line 670 are formedon the first surface 610A. In some embodiments, the processing unit 600is electrically connected to the display signal line 650A of the gatedriver circuit 650 through the multiple first connective portions 620and the first conductive layer 631. The signal of the processing unit600 is further transmitted to the data line 670, which extends alongfirst direction (Y direction), through the output signal circuit 650B ofthe gate driver circuit 650. In this embodiment, the extending directionof the first connective portion 620 is perpendicular to the firstdirection and the second direction.

Referring to FIGS. 6C-6E, FIG. 6C is a cross-sectional view taken alongline C-C′, FIG. 6D is a cross-sectional view taken along line D-D′, andFIG. 6E is a cross-sectional view taken along line E-E′ of the displaydevice 5000 shown in FIG. 6B, in accordance with some embodiments. Asshown in FIG. 6C, a first insulation layer 700 is disposed on the firstconductive layer 631, a second insulation layer 690 is disposed on thefirst insulation layer 700, and the data line 670 is disposed on thesecond insulation layer 690. As shown in FIG. 6D, a second connectiveportion 651 is at least partially disposed in the first insulation layer700 and penetrates through the first insulation layer 700. The displaysignal line 650A is disposed on the first insulation layer 700. The gatedriver circuit 650 is electrically connected to the first conductivelayer 631. For example, the display signal line 650A of the gate drivercircuit 650 is electrically connected to the first conductive layer 631through the second connective portion 651. As shown in FIG. 6E, thesecond connective portion 651 is disposed in the first insulation layer700 and the second insulation layer 690, and penetrates through thefirst insulation layer 700 and the second insulation layer 690. The dataline 670 is electrically connected to the first conductive layer 631through the second connective portion 651.

Referring to FIG. 6C, in some embodiments, the (greatest) width of thefirst conductive layer 631 along the C-C′ direction is greater than the(greatest) width of the first connective portion 620 along the C-C′direction, and the (greatest) width of the second conductive layer 632along the C-C′ direction is greater than the (greatest) width of thefirst connective portion 620 along the C-C′ direction. The firstconductive layer 631 and second conductive layer 632 may be used asconductive pads, and it can ensure good conductive effectiveness with agreater width. In some embodiments, the position of the processing unit600 corresponds to that of the first connective portion 620. Forexample, from a view along a direction perpendicular to the firstsurface 610A of the substrate 610, the processing unit 600 at leastpartially overlaps the first connective portion 620, and the firstconnective portion 620 at least partially overlaps the first conductivelayer 631 or the second conductive layer 632.

FIG. 6F is a variation of the display device 5000 shown in FIG. 6B. Asshown in FIG. 6F, the display device 5000 further includes ademultiplexer 660 which is disposed on the first surface 610A andelectrically connected to the first conductive layer 631. One signalline from the processing unit 600 may be selectively distributed to oneof multiple outputs through the demultiplexer 660. For example, as shownin FIG. 6F, one signal line from the processing unit 600 may beselectively distributed to one of three data lines through thedemultiplexer 660. In FIG. 6B, three first connective portions 620 areneeded to correspond to the three data lines. With the design of FIG.6F, just one connective portion 620 is needed to correspond to the threedata lines 670. As a result, the number of required first connectiveportions 620 is reduced. The description of the cross-sectional view ofFIG. 6F is similar to that of FIGS. 6C-6E, and is omitted for brevity.

Referring to FIG. 7A, FIG. 7A is a cross-sectional view of a displaydevice 6000, in accordance with other embodiments. The display device6000 includes a processing unit 710, a substrate 740 and a displayelement layer 750. The substrate 740 has a first surface 740A and asecond surface 740B opposite to the first surface 740A. The displayelement layer 750 is disposed on the first surface 740A. A firstconductive layer 721 is disposed on the first surface 740A, and a secondconductive layer 722 is disposed on the second surface 740B. Theprocessing unit 710 is disposed on the second surface 740B andelectrically connected to the second conductive layer 722. The firstconnective portion 730 is at least partially disposed in the substrate740, and penetrates from the first surface 740A to the second surface740B. The first conductive layer 721 is electrically connected to thesecond conductive layer 722 by the first connective portion 730, andthereby the signal of the processing unit 710 is transmitted to thedisplay element layer 750.

In this embodiment, from a direction perpendicular to the first surface740A of the substrate 740, the processing unit 710 does not overlap withthe first connective portion 730. That is to say, the processing unit740 is separated from the first connective portion 730 from a view inthe direction perpendicular to the first surface 740A of the substrate740. The processing unit 710 is electrically connected to the firstconnective portion 730 through a wire 720 and the second conductivelayer 722, and the first connective portion 730 is electricallyconnected to the display element layer 750 through the first conductivelayer 721.

Referring to FIG. 7B, FIG. 7B is a top view of a circuit layout of thedisplay device 6000 shown in FIG. 7A, in accordance with someembodiments. It should be noted that FIG. 7B only illustrates theprocessing unit 710, the wire 720, the first connective portion 730 andother circuits disposed in the display element layer 750 for brevity. Asshown in FIG. 7B, the display element layer 750 includes a gate drivercircuit 760 and a data line 780. The gate driver circuit 760 includes adisplay signal line 760A (such as an input signal circuit) extendingalong a first direction (such as Y direction) and an output signalcircuit 760B (such as a scan line) extending along a second direction(such as X direction). In some embodiments, the processing unit 710 iselectrically connected to a first connective portion 730 throughmultiple wires 720. In this embodiment, the processing unit 710 iselectrically connected to the display signal line 760A of the gatedriver circuit 760 through the wires 720, and subsequently through thefirst connective portion 730.

Referring to FIGS. 7C-7E, FIG. 7C is a cross-sectional view taken alongline F-F′, FIG. 7D is a cross-sectional view taken along line G-G′, andFIG. 7E is a cross-sectional view taken along line H-H′ of the displaydevice 6000 shown in FIG. 7B, in accordance with some embodiments. Asshown in FIG. 7D, a first insulation layer 790 is disposed on the firstconductive layer 721, and a second connective portion 751 is at leastpartially disposed in the first insulation layer 790 and penetratesthrough the first insulation layer 790. The display signal line 760A isdisposed on the first insulation layer 790. The gate driver circuit 760is electrically connected to the first conductive layer 721. Forexample, the display signal line 760A of the gate driver circuit 760 iselectrically connected to the first conductive layer 721 through thesecond connective portion 751.

As shown in FIG. 7E, a second insulation layer 800 is disposed on thefirst insulation layer 790. The second connective portion 751 isdisposed in the first insulation layer 790 and the second insulationlayer 800, and penetrates the first insulation layer 790 and the secondinsulation layer 800. A data line 780 is electrically connected to thefirst conductive layer 721 through the second connective portion 751. Insome embodiments, the first connective portion 730 at least partiallyoverlaps the second connective portion 751. As shown in FIGS. 7A and 7C,from a direction perpendicular to the substrate 740, the firstconnective portion 730 is not disposed directly on the processing unit710, and the processing unit 710 is electrically connected to the firstconnective portion 730 through the wires 720.

FIG. 7F is a variation of the display device 6000 shown in FIG. 7B. Asshown in FIG. 7F, the display device 6000 further includes ademultiplexer 770 which is disposed on the second surface 740B of thesubstrate 740, and electrically connected to the second conductive layer722. One signal line from the processing unit 710 may be selectivelydistributed to one of multiple outputs through the demultiplexer 770.For example, as shown in FIG. 7F, one signal line from the processingunit 710 may be selectively distributed to one of three data linesthrough the demultiplexer 770. In FIG. 7B, three first connectiveportions 730 are needed to correspond to the three data lines. With thedesign of FIG. 7F, just one connective portion 730 is needed tocorrespond to the three data lines 780. As a result, the required numberof first connective portions 730 is reduced. The description of thecross-sectional view of FIG. 7F is similar to that of FIGS. 7C-7E, andis omitted for brevity.

Referring to FIG. 8, FIG. 8 is a circuit diagram of a demultiplexer 820,in accordance with some embodiments. The demultiplexer 660 shown inFIGS. 6F and the demultiplexer 770 shown in 7F may have the circuitdiagram of the demultiplexer 820 shown in FIG. 8. The diagram and theprinciple of the demultiplexer 660 are similar to those of thedemultiplexer 770, and the following description uses the demultiplexer660 shown in FIG. 6F as an example. As shown in FIG. 8, the processingunit 810 is coupled to the first connective portions A, B, C, D1, D2˜Dnand G1˜Gn. The first connective portions A, B, C may be used as a clockgenerator of the demultiplexer 820. The first connective portion D1 iscoupled to the source of the data lines Y0, Y1 and Y2, and the firstconnective portion D2 is coupled to the source of the data lines Y3, Y4and Y5. In some embodiments, there are n first connective portionscoupled to the source of the data lines, and this only illustrates thedata lines corresponding to the first connective portions D1 and D2, forbrevity. The first connective portions G1˜Gn are coupled to the source(not shown) of the gate driver circuit. As shown in FIG. 8, the firstconnective portion A is coupled to the gate of the data lines Y0 and Y3,the first connective portion B is coupled to the gate of the data linesY1 and Y4, and the first connective portion C is coupled to the gate ofthe data lines Y2 and Y5. In this embodiment, one first connectiveportion D1 may be used to control the switching of three data lines Y0,Y1 and Y2 by a signal combination of the clock generator (namely, thefirst connective portions A, B and C). Therefore, the number of requiredfirst connective portions is reduced.

In some embodiments, the processing unit is disposed on the back side ofthe substrate. In some embodiments, the processing unit on the back sideof the substrate can be electrically connected to the display elementlayer on the front side, by using the first connective portionpenetrating the substrate, and thus the signal is transmitted.Therefore, the processing unit does not occupy additional area on thefront side of the substrate, and a display device that has a narrowborder or is borderless is formed.

Referring to FIG. 9, FIG. 9 is a top view of a display device 2000, inaccordance with some embodiments. It should be noted that FIG. 9 onlyillustrates a pixel driver circuit 370, a gate driver circuit 290 and aprocessing unit 270 of the display device 2000 for showing thearrangement of every element clearly. As shown in FIG. 9, the gatedriver circuit 290 is disposed on two sides of the display device 2000,and extends along the first direction (Y direction). The processing unit270 may be disposed on another side that is different from the sides onwhich the gate driver circuit 290 is disposed, and the processing unit270 may be disposed between two gate driver circuits 290 and extendalong the second direction (X direction). Although FIG. 9 illustratestwo gate driver circuits, according to other embodiments, the displaydevice 2000 can also include only one gate driver circuit.

Referring to FIG. 10A, FIG. 10A is a cross-sectional view taken alongline A-A′ of the display device 2000 shown in FIG. 9, in accordance withsome embodiments. As shown in FIG. 10A, the gate driver circuit 290 isdisposed on the substrate 120, and on two sides of the substrate 120. Insome embodiments, the pixel driver circuit 370 and the gate drivercircuit 290 are in different layers. For example, the pixel drivercircuit 370 and the gate driver circuit 290 may be disposed on the firstsurface 120A of the substrate 120, and the pixel driver circuit 370 isdisposed on the gate driver circuit 290. In this embodiment, a space 300among the pixel driver circuit 370, the substrate 120 and the gatedriver circuit 290 may be used to dispose the circuits of otherelectronic elements therein. In some embodiments, the space 300 is usedto dispose touch circuits or sensing circuits therein.

Referring to FIG. 10B, FIG. 10B is a cross-sectional view taken alongline B-B′ of the display device 2000 shown in FIG. 9, in accordance withsome embodiments. As shown in FIG. 10B, the processing unit 270 isdisposed on the second surface 120B of the substrate 120. In someembodiments, the processing unit 270 at least partially overlaps thefirst connective portion 240B. For example, the processing unit 270 isdisposed directly under the first connective portion 240B, the firstconductive layer 251 and the second conductive layer 252. In otherembodiments, the processing unit 270 is not disposed directly under thefirst connective portion 240B. The processing unit 270 may beelectrically connected to the first connective portion 240B throughadditional wires (not shown). For example, the processing unit can applythe connection as shown in FIG. 7A, and the processing unit 710 iselectrically connected to the first connective portion 730 through thewires 720 as shown in FIG. 7A. Namely, in FIG. 10B, the processing unit270 may be electrically connected to the first connective portion 240Bthrough the wires (such as the wires 720, not shown) and the secondconductive layer 252. In some embodiments, the processing unit 270,which is disposed on the second surface 120B of the substrate 120, maybe electrically connected to the gate driver circuit 290, which isdisposed on the first surface 120A of the substrate 120, through thefirst connective portion 240B. In some embodiments, the processing unit270, which is disposed on the second surface 120B of the substrate 120,may be electrically connected to the touch circuits or the sensingcircuits, which is disposed on the first surface 120A of the substrate120, through the first connective portion 240B. In some embodiments, thetouch circuits or the sensing circuits are disposed in the space 300.

In some embodiments, the gate driver circuit 290 at least partiallyoverlaps the pixel circuit 370. With this arrangement, the gate drivercircuit 290 does not occupy additional area on the substrate, andthereby a display device 2000 that has a narrow border or is borderlessis formed. In some embodiments, the processing unit 270 is disposed onthe second surface 120B of the substrate 120. Therefore, the processingunit 270 does not occupy additional area on the substrate, and thereby adisplay device 2000 that has a narrow border or is borderless is formed.

Referring to FIG. 11A, FIG. 11A is a detailed circuit diagram of a part2000P of the display device 2000 shown in FIG. 10A, in accordance withsome embodiments. FIG. 11A only illustrates a part 2000P of the displaydevice 2000, and the part 2000P includes a portion of the gate drivercircuit 290, the pixel driver circuit 370 and a light-emitting element550. The gate driver circuit 290, the pixel driver circuit 370 and thelight-emitting element 550 may be disposed on the first surface 120A ofthe substrate 120. The pixel driver circuit 370 may include, but is notlimited to, thin film transistors T1, T2 and T3. The thin filmtransistor T1 may be a switch transistor, the thin film transistor T2may be a driver transistor and the thin film transistor T3 may be areset transistor. The gate driver circuit may include, but is notlimited to, an output transistor T4. Although it only illustrates threethin film transistors of the pixel driver circuit 370 in FIG. 11A, thoseskilled in the art know that the pixel driver circuit may include moretransistors to meet practical needs.

The first conductive layer 251 is disposed on the first surface 120A ofthe substrate 120 and the second conductive layer 252 is disposed on thesecond surface 120B of the substrate 120. The first conductive layer 251may include a first part 251 a and a second part 251 b. The first part251 a may be disposed (directly) under the output transistor T4, and maybe used to block a semiconductor layer 303 of the output transistor T4from light. The second part 251 b of the first conductive layer 251 maybe disposed in a position corresponding to the first connective portion240B, and electrically connected to the processing unit 270 through thefirst connective portion 240B. In some embodiments, the first part 251 aand the second part 251 b are formed in the same layer. In the presentdisclosure, the A layer and the B layer are the same layer, which meansthat the A layer and the B layer may be formed of the same material andpatterned in the same process. Namely, the first part 251 a and thesecond part 251 b are formed of the same conductive material and arepatterned in the same process.

In FIG. 11A, the processing unit 270 is disposed in the correspondingposition to the first connective portion 240B. Namely, the processingunit 270 at least partially overlaps the first connective portion 240B.However, in other embodiments, the processing unit 270 does not overlapwith the first connective portion 240B. For example, the processing unit270 may be electrically connected to the first connective portion 240Bthrough the wires (such as the wires 720 similar to FIG. 7A, not shown)and the second conductive layer 252 as shown in FIG. 7A.

An insulation layer 320 is disposed on the first conductive layer 251.The output transistor T4 is disposed on the insulation layer 320 and mayinclude the semiconductor layer 303, a gate layer 350, and asource/drain layer 306SD. The semiconductor layer 303 is disposed on theinsulation layer 320, an insulation layer 325A is disposed between thegate layer 350 and the semiconductor layer 303, and an insulation layer325B is disposed between the gate layer 350 and the source/drain layer306SD. The semiconductor layer 303 may include, but is not limited to, achannel region 340 and a doped region 330.

In some embodiments, the transistor of the gate driver circuit 290 andthe transistor of the pixel driver circuit 370 may have the same layer.For example, as shown in FIG. 11A, the source/drain layer 306SD of theoutput transistor T4 and the gate 306G of the transistors T1, T2 and T3of the pixel driver circuit 370 are in the same layer. Namely, thesource/drain layer 306SD of the output transistor T4 and the gate 306Gof the transistors T1, T2 and T3 are formed in the same conductive layerand patterned in the same process.

The transistor T4 is electrically connected to the switch transistor T1so that the signal of the gate driver circuit 290 is transmitted to theswitch transistor T1. The switch transistor T1 may be electricallyconnected to the driver transistor T2. FIG. 11A illustrates thetransistor T4 of the gate driver circuit 290 as a top gate transistor,and the transistors T1, T2 and T3 of the pixel driver circuit 370 asbottom gate transistors. In other embodiments, the transistor T4 mayalso be a bottom gate transistor, and the transistors T1, T2 and T3 mayalso be top gate transistors. The active layer of the transistors T1,T2, T3 and T4 may be a semiconductor such as amorphous silicon,polysilicon or a metal oxide. The metal oxide may be indium gallium zincoxide (IGZO). In some embodiments, the active layer 400 of thetransistors T1, T2, T3 may be IGZO, and the active layer 303 of thetransistors T4 may be polysilicon.

The light-emitting element 550 may be disposed on the pixel drivercircuit 370. Insulation layers 410 and 430 may be disposed between thelight-emitting element 550 and the pixel driver circuit 370. Thelight-emitting element 550 includes a first electrode 440, alight-emitting layer 450 and a second electrode 460. The light-emittinglayer 450 is disposed between the first electrode 440 and the secondelectrode 460, and in an opening of the pixel definition layer 435. Thesecond electrode 460 may cover the pixel definition layer 435. The firstelectrode 440 may be an anode, and the second electrode may be acathode. Alternatively, the first electrode 440 may be a cathode, andthe second electrode may be an anode. The first electrode 440 of thelight-emitting element 550 may be electrically connected to the drivertransistor T2 through a connective via 550C which may be formed in theinsulation layers 410 and 430.

In some embodiments, the light-emitting layer 450 includes an organiclight-emitting diode, and thereby the display device 2000 is used as anorganic light-emitting diode display device. In some embodiments, thelight-emitting layer 450 includes an inorganic light-emitting diode suchas a micro light-emitting diode, and thereby the display device 2000 isused as a micro light-emitting diode display device.

Referring to FIG. 11B, FIG. 11B is a part 2000P of the top view of adisplay device shown in FIG. 11A, in accordance with some embodiments.FIG. 11B illustrates the gate driver circuit 290, the pixel drivercircuit 370, the light-emitting layer 450 and the substrate 120 with thequadrangles for showing the arrangement of the layout clearly. FIG. 11Bonly illustrates a part of the pixel driver circuit 370. The projectionof the gate driver circuit 290 on the first surface 120A of thesubstrate 120 is referred to as a first projection P1, the projection ofthe pixel driver circuit 370 on the first surface 120A of the substrate120 is referred to as a second projection P2, and the projection of thelight-emitting layer 450 on the first surface 120A of the substrate 120is referred to as a third projection P3. In some embodiments, in thepart 2000P of the display device shown in FIG. 11B, the first projectionP1 at least partially overlaps the second projection P2. In someembodiments, the third projection P3 at least partially overlaps thesecond projection P2, and the first projection P1 is separated from thethird projection P3.

Referring to FIG. 12, FIG. 12 is a detailed circuit diagram of the part2000P of the display device shown in FIG. 10A, in accordance with otherembodiments. FIG. 12 is a variation of FIG. 11A. One of the differencesbetween FIG. 12 and FIG. 11A is that the display device further includesa conductive portion 350A formed between the insulation layer 325A andthe insulation layer 325B. The gate driver circuit 290 may beelectrically connected to the reset transistor T3 through the conductiveportion 350A and a connective via 360C (formed in the insulation layer325B). The conductive portion 350A and the gate layer 350 of the outputtransistor T4 may be in the same layer.

Referring to FIG. 13, FIG. 13 is a detailed circuit diagram of the part2000P of the display device 2000 shown in FIG. 10A, in accordance withother embodiments. FIG. 13 is a variation of FIG. 11A. One of thedifferences between FIG. 13 and FIG. 11A is that the gate 308G of thedriver transistor T2 and the gate 306G of the reset transistor T3 are indifferent layers. The gate 308G is separated from the gate 306G by aninsulation layer 691. An insulation layer 692 is disposed between theactive layer 400 and the gate 308G. The gate 306G of the resettransistor T3 and the source/drain 306SD of the output transistor T4 maybe the in same layer.

Referring to FIG. 14A, FIG. 14A is a detailed circuit diagram of thepart 2000P of the display device 2000 shown in FIG. 10A, in accordancewith other embodiments. FIG. 14A is a variation of FIG. 11A. One of thedifferences between FIG. 14A and FIG. 11A is that the position of thelight-emitting layer 450 at least partially overlaps the gate drivercircuit 290, and the position of the light-emitting layer 450 isseparated from the pixel driver circuit 370. Namely, as shown in a topview of FIG. 14B, the third projection P3 at least partially overlapsthe first projection P1, and the third projection P3 is separated fromthe second projection P2.

Referring to FIG. 15A, FIG. 15A is a detailed circuit diagram of thepart 2000P of the display device 2000 shown in FIG. 10A, in accordancewith other embodiments. FIG. 15A is a variation of FIG. 11A. One of thedifferences between FIG. 15A and FIG. 11A is that the pixel drivercircuit 370, the gate driver circuit 290 and the light-emitting layer450 are at least overlapping each other simultaneously. Namely, as shownin a top view of FIG. 15B, a portion of the first projection P1, aportion of the second projection P2 and a portion of the thirdprojection P3 are at least overlapped to each other.

FIG. 16 is a part of a cross-sectional view of a display device 4000, inaccordance with some embodiments. The display device 4000 is a touchdisplay device. FIG. 16 has elements that are similar to FIG. 11A. Forexample, the display device 4000 shown in FIG. 16 includes a pixeldriver circuit 370, a light-emitting element 550, a processing unit 270,a first connective portion 240B, a first conductive layer 251, a secondconductive layer 252, etc. The pixel driver circuit 370 may include, butis not limited to, the switch transistor T1, the driver transistor T2,and the reset transistor T3, and the description is omitted. As shown inFIG. 16, the display device 4000 further includes an encapsulation layer500, a touch electrode 510A, a touch signal line 510B and a touchtransmission portion 520. The touch electrode 510A is disposed in thetouch region 4000A of the display device 4000. The touch signal line510B and the touch transmission portion 520 are disposed in theperipheral region 4000B (non-touch region) of the display device 4000.

The encapsulation layer 500 is disposed on the light-emitting element550, and the touch electrode 510A and the touch signal line 510B aredisposed on the encapsulation layer 500. The encapsulation layer 500 mayinclude a multiple layers structure, such as a structure that includesinorganic layer/organic layer/inorganic layer. The touch electrode 510Aand the touch signal line 510B are disposed on the first surface 120A ofthe substrate 120. The touch electrode 510A is electrically connected tothe first conductive layer 251 through the touch signal line 510B andthe touch transmission portion 520. As a result, the signal from theprocessing unit 270 is transmitted to the touch signal line 510B throughthe first connective portion 240B and the touch transmission portion520.

The material of the touch electrode 510A may be the same as or differentfrom that of the touch signal line 510B. The material of the touchelectrode 510A and the touch signal line 510B may include, but is notlimited to, indium tin oxide (ITO), tin oxide (SnO), indium zinc oxide(IZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO),antimony tin oxide (ATO), antimony zinc oxide (AZO), metal, or acombination thereof.

The touch transmission portion 520 may include a first touchtransmission 306A, a second touch transmission 380A and a third touchtransmission 440A. In some embodiments, for simplifying the process, thefirst touch transmission 306A, the second touch transmission 380A andthe third touch transmission 440A may be the same layer as the electrodelayer of the transistor of the pixel driver circuit 370, or the samelayer as the electrode layer of the light-emitting layer 550. Forexample, as shown in FIG. 16, the first transmission portion 306A may bethe same layer as the gate 306G of the transistors (T1, T2 or T3) of thepixel driver circuit 370, and the second transmission portion 380A maybe the same layer as the source/drain 380SD of the transistors (T1, T2or T3). The third transmission portion 440A may be the same layer as thefirst electrode 440 of the light-emitting element 550. The touchelectrode 510A is electrically connected to the first conductive layer251 through the touch signal line 510B and the touch transmissionportion 520.

Referring to FIG. 17, FIG. 17 is a cross-sectional view of a displaydevice 4000, in accordance with some embodiments. FIG. 17 is a variationof FIG. 16. One of the differences between FIG. 17 and FIG. 16 is thatthe display device 4000 further includes a touch signal line 530 and aconnective portion 530A. The touch signal line 530 may be disposedbetween the insulation layer 325A and the insulation layer 325B, and theconnective portion 530A may penetrate through the insulation layer 325Aand the insulation layer 320. The touch electrode 510A is electricallyconnected to the first conductive layer 251 through the touch signalline 510B, the touch transmission portion 520, the touch signal line 530and the connective portion 530A.

Referring to FIG. 18, FIG. 18 is a cross-sectional view of a displaydevice 4000, in accordance with some embodiments. FIG. 18 is a variationof FIG. 16. One of the differences between FIG. 18 and FIG. 16 is thatthe display device 4000 shown in FIG. 18 further includes a conductiveink 540 disposed between the touch signal line 510B and the thirdtransmission portion 440A. The conductive ink 540 may penetrate throughthe encapsulation layer 500 and a portion of the pixel definition layer435.

In some embodiments, the processing unit is disposed on the backside ofthe substrate. In some embodiments, the processing unit disposed on thebackside of the substrate is electrically connected to the displayelement layer or the touch electrode layer disposed on the front side ofthe substrate through the first connective portion penetrating thesubstrate, and thereby the signal from the processing unit istransmitted. Therefore, the processing unit does not occupy additionalarea on the front side of the substrate. As a result, a display devicethat has narrow border or is borderless is formed. In some embodiments,the gate driver circuit at least partially overlaps the pixel drivercircuit. Therefore, the gate driver circuit does not occupy additionalarea on the substrate, and a display device that has a narrow border oris borderless is formed.

Although some embodiments of the present disclosure and their advantageshave been described in detail, it should be understood that variouschanges, substitutions and alterations can be made herein withoutdeparting from the spirit and scope of the disclosure as defined by theappended claims. For example, it will be readily understood by thoseskilled in the art that many of the features, functions, processes, andmaterials described herein may be varied while remaining within thescope of the present disclosure. Moreover, the scope of the presentapplication is not intended to be limited to the particular embodimentsof the process, machine, manufacture, composition of matter, means,methods and steps described in the specification. As one of ordinaryskill in the art will readily appreciate from the disclosure of thepresent disclosure, processes, machines, manufacture, compositions ofmatter, means, methods, or steps, presently existing or later to bedeveloped, that perform substantially the same function or achievesubstantially the same result as the corresponding embodiments describedherein may be utilized according to the present disclosure. Accordingly,the appended claims are intended to include within their scope suchprocesses, machines, manufacture, compositions of matter, means,methods, or steps.

What is claimed is:
 1. A display device, comprising: a substrate havinga first surface and a second surface opposite to the first surface; afirst conductive layer disposed on the first surface; a secondconductive layer disposed on the second surface; a processing unitdisposed on the second surface and is electrically connected to thesecond conductive layer; and a first connective portion at leastpartially disposed in the substrate, and penetrating from the firstsurface to the second surface, wherein the first conductive layer iselectrically connected to the second conductive layer through the firstconnective portion.
 2. The display device as claimed in claim 1, furthercomprising: a demultiplexer disposed on the first surface andelectrically connected to the first conductive layer.
 3. The displaydevice as claimed in claim 1, further comprising: a demultiplexerdisposed on the second surface and electrically connected to the secondconductive layer.
 4. The display device as claimed in claim 1, furthercomprising: a gate driver circuit disposed on the first surface andelectrically connected to the first conductive layer.
 5. The displaydevice as claimed in claim 4, further comprising: a display signal linedisposed on the first surface, wherein the gate driver circuit iselectrically connected to the first conductive layer through the displaysignal line.
 6. The display device as claimed in claim 5, furthercomprising: a first insulation layer disposed on the first conductivelayer; and a second connective portion at least partially disposed inthe first insulation layer, and penetrating through the first insulationlayer, wherein the display signal line is disposed on the firstinsulation layer, and electrically connected to the first conductivelayer through the second connective portion.
 7. The display device asclaimed in claim 6, wherein the processing unit at least partiallyoverlaps the first connective portion.
 8. The display device as claimedin claim 6, wherein the first connective portion at least partiallyoverlaps the second connective portion.
 9. The display device as claimedin claim 4, further comprising: a pixel driver circuit disposed on thefirst surface of the substrate, wherein the gate driver circuit has afirst projection on the first surface, the pixel driver circuit has asecond projection on the first surface, and the first projection atleast partially overlaps the second projection.
 10. The display deviceas claimed in claim 9, further comprising: a light-emitting elementdisposed on the first surface, wherein the light-emitting elementcomprises a light-emitting layer, and the light-emitting layer has athird projection on the first surface.
 11. The display device as claimedin claim 10, wherein the second projection at least partially overlapsthe third projection, and the first projection is separated from thethird projection.
 12. The display device as claimed in claim 10, whereina portion of the first projection, a portion of the second projectionand a portion of the third projection are at least overlapped to eachother.
 13. The display device as claimed in claim 1, further comprising:a touch electrode disposed on the first surface; and a touch signal linedisposed on the first surface, wherein the touch electrode iselectrically connected to the first conductive layer through the touchsignal line.
 14. The display device as claimed in claim 1, wherein thefirst connective portion has a first width along the first surface and asecond width along the second surface, and the first width is differentfrom the second width.
 15. The display device as claimed in claim 1,wherein the first connective portion has a first width along the firstsurface and a third width along a reference plane, wherein the referenceplane is located between the first surface and the second surface andparallel to the first surface, and wherein the first width is differentfrom the third width.